Neso Academy Digital Electronics: study plan and how long it takes
The Neso Academy playlist is 202 videos and 29.7 hours long. Here's how long it takes at different paces, a week-by-week schedule built from the real videos, and a planner that turns it into your own daily plan.
202 videos · 29.7 hours · Neso Academy
Neso Academy's Digital Electronics course is one of the most complete on YouTube: number systems and codes, Boolean algebra, K-maps, combinational circuits like adders and multiplexers, flip-flops and conversions, counters and registers, and programmable logic devices.
At over 200 videos it's long, but each video is short and focused on a single idea.
Who it's for: Electronics and CS students, and GATE aspirants in ECE, EE and CS.
How long does it take?
The full playlist is 29.7 hours across 202 videos. Here's roughly how many days that is at different daily watch times and speeds, counting video time only:
| Daily time | At 1x | At 1.5x | At 2x |
|---|---|---|---|
| 30 min a day | 60 days | 40 days | 30 days |
| 1 h a day | 30 days | 20 days | 15 days |
| 2 h a day | 15 days | 10 days | 8 days |
Make your own schedule
The playlist link is already filled in. Press Plan, set how much time you have each day and your speed, and you'll get a day-by-day schedule with a finish date and a calendar file. It reads the live playlist, so new videos are included.
Week-by-week schedule
A sample plan at 1 hour a day and normal speed, using whole videos so none is split across days. That's 5 weeks in total. For a different pace, start date or speed, use the planner above.
Week 1Videos 1–49 · 6h 15m
Day 1 · 48m
- 1What is Signal?9m
- 2What is an Analog Signal?9m
- 3What is Digital Signal?9m
- 4Need of Digital Signals5m
- 5Introduction to Digital Electronics7m
- 6Switch and Bits Intuition10m
Day 2 · 49m
- 7Introduction to Boolean Algebra (Part 1)18m
- 8Introduction to Boolean Algebra (Part 2)10m
- 9Boolean Algebra Examples (Part 1)8m
- 10Boolean Algebra Examples (Part 2)6m
- 11Redundancy Theorem (Boolean Algebra Trick)8m
Day 3 · 59m
- 12Sum of Products (Part 1) | SOP Form13m
- 13Sum of Products (Part 2) | SOP Form8m
- 14Product of Sums (Part 1) | POS Form11m
- 15Product of Sums (Part 2) | POS Form6m
- 16SOP and POS Form Examples13m
- 17Minimal to Canonical Form Conversion (Part 1)9m
Day 4 · 55m
- 18Minimal to Canonical Form Conversion (Part 2)5m
- 19Examples & Tricks (SOP and POS Forms)12m
- 20Positive and Negative Logic5m
- 21Dual Form10m
- 22Self Dual10m
- 23Complement Meaning and Examples7m
- 24Venn Diagram6m
Day 5 · 52m
- 25Switching Circuits (Part 1)11m
- 26Switching Circuits (Part 2)12m
- 27Statement Problems in Boolean Algebra (Part 1)4m
- 28Statement Problems in Boolean Algebra (Part 2)7m
- 29Introduction to Number Systems9m
- 30Binary Number System8m
Day 6 · 55m
- 31Decimal to Binary Conversion10m
- 32Decimal to Octal Conversion5m
- 33Decimal to Hexadecimal Conversion6m
- 34Binary to Decimal Conversion6m
- 35Octal to Decimal Conversion6m
- 36Hexadecimal to Decimal Conversion5m
- 37Octal to Binary & Binary to Octal Conversion6m
- 38Hexadecimal to Binary & Binary to Hexadecimal Conversion7m
- 39Hexadecimal to Octal & Octal to Hexadecimal Conversion5m
Day 7 · 56m
- 40Binary Addition8m
- 41Binary Subtraction5m
- 42Binary Multiplication8m
- 43Binary Division6m
- 44Octal Addition6m
- 45Octal Subtraction3m
- 46Octal Multiplication5m
- 47Hexadecimal Addition6m
- 48Hexadecimal Subtraction4m
- 49Hexadecimal Multiplication6m
Week 2Videos 50–84 · 6h 7m
Day 8 · 52m
- 50r's Complement6m
- 51(r-1)'s Complement8m
- 521's and 2's Complement5m
- 53Shortcut for 2's Complement3m
- 54Data Representation using Signed Magnitude6m
- 55Data Representation using 1's Complement3m
- 56Data Representation using 2's Complement8m
- 57Binary Subtraction using 1's Complement12m
Day 9 · 56m
- 58Binary Subtraction using 2's Complement13m
- 59Classification of Codes8m
- 60Binary Coded Decimal (BCD) Code17m
- 61BCD Addition14m
- 62Shift Add 3 Method | Simple method for Binary to BCD conversion5m
Day 10 · 58m
- 632421 Code9m
- 64Excess-3 Code (XS-3 Code)12m
- 65Excess-3 Code Addition10m
- 66Introduction to Gray Code6m
- 67Binary to Gray Code Conversion7m
- 68Gray Code to Binary Conversion6m
- 69What is Parity?9m
Day 11 · 49m
- 70Hamming Code | Error Detection12m
- 71Hamming Code | Error Correction6m
- 72Logic Gates (Part 1)16m
- 73Logic Gates (Part 2)14m
Day 12 · 57m
- 74Logic Gates (Part 3)13m
- 75Logic Gates (Part 4)11m
- 76Logic Gates (Part 5) | Important!20m
- 77Logic Gates (Part 6) | Important!14m
Day 13 · 36m
- 78NAND Gate as Universal Gate (Part 1)9m
- 79NAND Gate as Universal Gate (Part 2)12m
- 80NOR Gate as Universal Gate14m
Day 14 · 1h
- 81Karnaugh Map (K' Map) - Part 126m
- 82Karnaugh Map (K' Map) - Part 214m
- 83Karnaugh Map (K' Map) - Part 311m
- 84K' Map and Implicants9m
Week 3Videos 85–127 · 6h 11m
Day 15 · 50m
- 854 Variable Karnaugh Map (Part 1)11m
- 864 Variable Karnaugh Map (Part 2)8m
- 874 Variable Karnaugh Map (Part 3)6m
- 88Don't Care in Karnaugh Map (K' Map)10m
- 89Don't Care in K' Map (Response to Doubt)6m
- 90K' Map using Max Terms (Part 1)8m
Day 16 · 54m
- 91K' Map using Max Terms (Part 2)11m
- 925 variables K' Map11m
- 93Quine-McCluskey Minimization Technique (Tabular Method)24m
- 94Digital Electronics Previous Year Solution of DRDO & ISRO (Part 2)8m
Day 17 · 52m
- 95Digital Electronics Previous Year Solution of DRDO & ISRO (Part 3)7m
- 964-Bit Even Parity Generator10m
- 97Seven Segment Display Decoder7m
- 98Seven Segment Display Decoder (Part 2)9m
- 99Seven Segment Display Decoder (Part 3)8m
- 100Comparison between Combinational and Sequential Circuits6m
- 101Half Adder5m
Day 18 · 57m
- 102Full Adder14m
- 103Full Adder using Half Adder7m
- 1044 Bit Parallel Adder using Full Adders10m
- 105Half Subtractor7m
- 106Full Subtractor | Easy Explanation8m
- 107Realizing Half Adder using NAND Gates only6m
- 108Realizing Half Adder using NOR Gates only5m
Day 19 · 49m
- 109Realizing Full Adder using NAND Gates only6m
- 110Realizing Half Subtractor using NAND Gates only7m
- 111Realizing Half Subtractor using NOR Gates only5m
- 112Realizing Full Subtractor using NAND Gates only (Part 1)9m
- 113Realizing Full Subtractor using NAND Gates only (Part 2)6m
- 1142-Bit Multiplier Using Half Adders10m
- 115Carry Lookahead Adder (Part 1) | CLA Generator6m
Day 20 · 58m
- 116Carry Lookahead Adder (Part 2) | CLA Adder11m
- 117BCD Adder | Simple Explanation15m
- 118Introduction to Multiplexers | MUX Basic12m
- 1194X1 Multiplexer6m
- 1208X1 Multiplexer6m
- 121MUX Tree Basic | 4X1 MUX using 2X1 MUX | Easy Explanation7m
Day 21 · 50m
- 122Implementing 8X1 MUX using 2X1 MUX5m
- 123Implementing 8X1 MUX using 4X1 MUX (Special Case)7m
- 12432X1 MUX using 8X1 MUX15m
- 125Implementation of Boolean Function using Multiplexers9m
- 1261-Bit Full Adder using Multiplexer9m
- 127Logical Expression from Multiplexer6m
Week 4Videos 128–173 · 6h 23m
Day 22 · 57m
- 128Introduction to Demultiplexer | 1:2 DEMUX10m
- 1291:4 Demultiplexer6m
- 130Full Subtractor using 1:8 Demultiplexer8m
- 131Demultiplexer as Decoder6m
- 1322-Bit Comparator6m
- 133Introduction to Encoders and Decoders7m
- 134Priority Encoder11m
- 135Decimal to BCD Encoder3m
Day 23 · 57m
- 136Octal to Binary Encoder5m
- 137Hexadecimal to Binary Encoder4m
- 138Full Adder Implementation using Decoder6m
- 139Practice Problems on Combinational Circuits (Part 1)12m
- 140Practice Problems on Combinational Circuits (Part 2)10m
- 141Practice Problems on Combinational Circuits (Part 3)11m
- 142Practice Problems on Combinational Circuits (Part 4)9m
Day 24 · 52m
- 143Introduction to Sequential Circuits | Important8m
- 144SR Latch | NOR and NAND SR Latch17m
- 145What is a Clock?6m
- 146Triggering Methods in Flip Flops5m
- 147How to get Edge Triggering | Simulation using Multisim11m
- 148Difference between Latch and Flip Flop6m
Day 25 · 53m
- 149Introduction to SR Flip Flop8m
- 150Truth Table, Characteristic Table and Excitation Table for SR Flip Flop9m
- 151Introduction to D flip flop5m
- 152Truth Table, Characteristic Table and Excitation Table for D Flip Flop4m
- 153Introduction to JK flip flop8m
- 154Truth Table, Characteristic Table and Excitation Table for JK flip flop10m
- 155Race Around Condition or Racing in JK Flip Flop9m
Day 26 · 55m
- 156Master Slave JK Flip Flop9m
- 157Behaviour of Master Slave D Flip Flop12m
- 158Introduction to T flip flop3m
- 159Truth Table, Characteristic Table and Excitation Table for T flip flop5m
- 1605 Steps for Flip Flop Conversions | JK to D Flip Flop Conversion7m
- 161T Flip Flop to D Flip Flop Conversion4m
- 162SR Flip Flop to JK Flip Flop Conversion8m
- 163SR Flip Flop to T Flip Flop Conversion6m
Day 27 · 49m
- 164Preset and Clear Inputs in Flip Flop6m
- 165Introduction to State Table, State Diagram & State Equation11m
- 166Design Procedure for Clocked Sequential Circuits19m
- 167Mealy and Moore State Machines (Part 1)10m
- 168Mealy and Moore State Machines (Part 2)4m
Day 28 · 1h
- 169Analysis of Clocked Sequential Circuits (with D Flip Flop)14m
- 170Analysis of Clocked Sequential Circuits (with JK Flip Flop)13m
- 171Analysis of Clocked Sequential Circuits (with T Flip Flop)9m
- 172Sequence or Pattern Detector9m
- 173Sequence Detector (Example)16m
Week 5Videos 174–202 · 4h 44m
Day 29 · 54m
- 174State Reduction and Assignment7m
- 175ASM Chart6m
- 176ASM Chart for Moore State Machine7m
- 177Difference between Synchronous and Asynchronous Sequential Circuits3m
- 178Introduction to Counters | Important12m
- 179Types of Counters | Comparison between Ripple and Synchronous counters7m
- 1803 Bit Asynchronous Up Counter12m
Day 30 · 51m
- 1814 Bit Asynchronous Up Counter10m
- 1823 bit & 4 bit Asynchronous Down Counter10m
- 1833 Bit & 4 Bit UP/DOWN Ripple Counter10m
- 184Modulus of the Counter & Counting up to Particular Value14m
- 185State Diagram of a Counter7m
Day 31 · 54m
- 186Decade (BCD) Ripple Counter9m
- 187How to Design Synchronous Counters | 2-Bit Synchronous Up Counter13m
- 1883-Bit Synchronous Up Counter12m
- 1893-Bit & 4-bit Up/Down Synchronous Counter20m
Day 32 · 48m
- 190Ring Counter14m
- 191Johnson's Counter (Twisted/Switch Tail Ring Counter)8m
- 192Introduction to Registers7m
- 193Data Formats and Classification of Registers7m
- 194Shift Register (SISO Mode)12m
Day 33 · 56m
- 195Shift Register (SIPO & PIPO Mode)12m
- 196Shift Register (PISO Mode)7m
- 197Bidirectional Shift Register8m
- 198Universal Shift Register16m
- 199Practice Problems on Sequential Circuits (Part 2)7m
- 200Practice Problems on Sequential Circuits (Part 3)6m
Day 34 · 20m
- 201Programmable Logic Array (PLA) | Easy Explanation11m
- 202Programmable Array Logic (PAL)10m
Tips for finishing
- Schedule it chapter by chapter with the planner's From and To fields instead of as one long course.
- Work through the practice problem videos; they're where the concepts turn into exam skills.