Gate Smashers Computer Organization and Architecture: study plan and how long it takes
The Gate Smashers playlist is 66 videos and 9.7 hours long. Here's how long it takes at different paces, a week-by-week schedule built from the real videos, and a planner that turns it into your own daily plan.
66 videos · 9.7 hours · Gate Smashers
Gate Smashers' COA playlist covers instruction types and formats, addressing modes, RISC vs CISC, cache memory and mapping techniques, cache replacement, pipelining and hazards, I/O interfaces and DMA, in short Hindi lectures.
At under 10 hours it's a quick way to cover a subject many students find dry.
Who it's for: GATE and university students who need to get through COA efficiently.
How long does it take?
The full playlist is 9.7 hours across 66 videos. Here's roughly how many days that is at different daily watch times and speeds, counting video time only:
| Daily time | At 1x | At 1.5x | At 2x |
|---|---|---|---|
| 30 min a day | 20 days | 13 days | 10 days |
| 1 h a day | 10 days | 7 days | 5 days |
| 2 h a day | 5 days | 4 days | 3 days |
Make your own schedule
The playlist link is already filled in. Press Plan, set how much time you have each day and your speed, and you'll get a day-by-day schedule with a finish date and a calendar file. It reads the live playlist, so new videos are included.
Week-by-week schedule
A sample plan at 1 hour a day and normal speed, using whole videos so none is split across days. That's 2 weeks in total. For a different pace, start date or speed, use the planner above.
Week 1Videos 1–44 · 6h 31m
Day 1 · 58m
- 1L-1.1: Computer Organization and Architecture Syllabus Discussion for GATE and UGC NTA NET14m
- 2L-1.2: Von Neumann's Architecture | Stored Memory Concept in Computer Architecture10m
- 3L-1.3:Various General Purpose Registers in Computer Organization and Architecture15m
- 4L-1.4:Types of Buses (Address, Data and Control) in Computer Organization and Architecture8m
- 5L-1.5: Common bus system using multiplexer | Computer organization and Architecture11m
Day 2 · 50m
- 6L-1.6: Common Bus system| How basic computer works19m
- 7L-1.7: Types of Instructions in General Purpose Computer | Computer Organization and Architecture5m
- 8L-1.8: Data Transfer Instructions in Computer Organisation and Architecture8m
- 9L-1.9: Arithmetic Instructions(Data Manipulation) in Computer Organisation and Architecture9m
- 10L-1.10: Logical Instructions(Data Manipulation) in Computer Organisation and Architecture9m
Day 3 · 59m
- 11L-1.11: Shift Instructions(Data Manipulation) in Computer Organisation and Architecture13m
- 12L-1.12: Program Control Instructions(Types of Control Instructions) | Computer Organization11m
- 13L-1.13: What is Instruction Format | Understand Computer Organisation with Simple Story11m
- 14L-1.14: Question on Instruction Format | Computer Organization | UGC NTA NET June 20219m
- 15L-1.15: Single Accumulator CPU Organisation | Single Address Instructions in Computer Organisation8m
- 16L-1.16: General Register CPU Organisation | Two and Three Address Instructions | COA7m
Day 4 · 59m
- 17L-1.17: Register Stack Organisation | Zero Address Instructions | COA12m
- 18L-1.18:Memory Stack Organisation | Memory stack Vs Register stack | COA6m
- 19L-2.1: What is Addressing Mode | Various Types of Addressing Modes | COA12m
- 20L-2.2: Implied Addressing Mode | Computer Organisation and Architecture5m
- 21L-2.3: Immediate Addressing Mode | Computer Organisation and Architecture7m
- 22L-2.4: Register Mode | Addressing Mode | Computer Organisation and Architecture5m
- 23L-2.5: Register Indirect Mode | Addressing Modes | Computer Organisation and Architecture6m
- 24L-2.6: Auto Increment and Decrement Addressing Modes | Computer Organisation and Architecture7m
Day 5 · 1h
- 25L-2.7: Direct Addressing Mode || Computer Organization and Architecture5m
- 26L-2.8: Indirect Addressing Mode | Computer Organisation and Architecture6m
- 27`L-2.9: Relative Addressing Mode || Computer Organisation and Architecture7m
- 28L-2.10: Base Register Addressing Mode || Computer Organisation and Architecture7m
- 29L-2.11: Indexed Addressing Mode || Computer Organisation and Architecture4m
- 30L-2.12: Question on Addressing Modes | Computer Organization5m
- 31L-2.13: RISC vs CISC | Computer Organization & Architecture8m
- 32L-3.1: Memory Hierarchy in Computer Architecture | Access time, Speed, Size, Cost | All Imp Points8m
- 33L-3.2: Independent vs Hierarchical Memory Organization | 2-Level Memory Organization10m
Day 6 · 51m
- 34L-3.3: 3-Level Memory Organisation || Computer Organisation and Architecture8m
- 35L-3.4: GATE 2004 Question on 3-Level Memory Organisation || Computer Organisation and Architecture6m
- 36L-3.5: What is Cache Mapping || Cache Mapping techniques || Computer Organisation and Architecture8m
- 37L-3.6: Direct Mapping with Example in Hindi | Cache Mapping | Computer Organisation and Architecture22m
- 38L-3.7: GATE 2005 Question on Direct Mapping | Cache Mapping Questions | Computer Organization7m
Day 7 · 53m
- 39L-3.8: Fully Associative Mapping with examples in Hindi | Cache Mapping | Computer Organisation10m
- 40L-3.9: Advantages and Disadvantages of Direct Mapping | Cache Mapping | Computer Organisation9m
- 41L-3.10: Set Associative Mapping with Examples in Hindi | Cache Mapping | Computer Organisation11m
- 42L-3.11: Locality of Reference in Cache Memory | Spatial Vs Temporal Locality | Computer Organization9m
- 43L-3.12: Cache Replacement Algorithms in Computer Organisation and Architecture6m
- 44L-3.13: LRU (Least Recently Used) Cache Replacement Algorithm | Computer Organisation & Architecture9m
Week 2Videos 45–66 · 3h 9m
Day 8 · 50m
- 45L-3.14: Gate 2014 Question on Set Associative Cache Mapping | Computer Organisation and Architecture8m
- 46L-3.15: FIFO Cache Replacement Policy with example | Computer Organisation and Architecture9m
- 47L-3.16: LRU(least recently used ) Cache Replacement Policy | Computer Organisation and Architecture8m
- 48L-4.1: Pipelining with real life example| Need of Pipelining | COA8m
- 49L-4.2: Pipelining Introduction and structure | Computer Organisation4m
- 50L-4.3: Pipelining Vs Non-Pipelining | Instruction Execution | Speedup, Efficiency, Utilization | COA13m
Day 9 · 57m
- 51L-4.4: Stage Delay in Pipeline | Previous Year GATE Question | Computer Organisation & Architecture11m
- 52L-4.5: Numerical Question on Pipelining | Previous year GATE Question | COA4m
- 53L-4.6: What is Hazard in Pipelining | various types of Hazards | computer Architecture10m
- 54L-4.7: Structural Hazards in Pipelining | Types of Hazards with Example in Hindi10m
- 55L-4.8: Control Hazards in Pipelining | Types of Hazards with Example in Hindi14m
- 56L-4.9: What is Read After Write(RAW) Hazards| Data Hazard in Pipelining with Example in Hindi | COA8m
Day 10 · 58m
- 57L-4.10: Write After Read Hazard with Example | Data Hazards| Computer Organization and Architecture9m
- 58L-4.11: Write After Write Hazard | Data Hazards in Pipelining | Computer Organization &&Architecture6m
- 59L-4.12: Register Renaming in Computer Organization | Data Hazard10m
- 60L-4.13: Operand Forwarding in Computer Organization & Architecture | Data Hazard11m
- 61I/O Interface in Computer Organization6m
- 62Interrupts in 8085 microprocessor | Types of Interrupts in Computer Organization10m
- 63Daisy Chaining in Priority Interrupt | Priority Based Interrupt in I/O Organization7m
Day 11 · 23m
- 64Parallel priority interrupt | I/O organization8m
- 65Question on Interrupt Handling(I/O organization) | Computer Organization | UGC NTA NET June 20219m
- 66Question on DMA (Direct Memory Access) | Input/Output Organization| COA | UGC NTA NET June 20217m
Tips for finishing
- Cache mapping and pipelining numericals carry the most marks. Do previous years' questions on both.
- Neso Academy's COA course has more solved problems if you need extra practice.